1. Field of the Invention
The present invention relates to a method for forming a field effect transistor upon a (100) silicon semiconductor substrate in a fashion whereby the completed transistor does not exhibit mask edge defects adjoining its gate spacer oxides. More particularly, the present invention relates to a method for implanting ions through a screening layer of varying thickness to form amorphous source/drain electrodes adjoining transistor gate spacer oxides, which amorphous source/drain electrodes when recrystallized will not exhibit mask edge defects at their junctures with the gate spacer oxides.
2. Description of Related Art
With the advent of advanced generations of semiconductor transistor technology, such as Very Large Scale Integrated (VLSI) circuit technology and Ultra Large Scale Integrated (ULSI) circuit technology, there is a substantial and continuing interest in understanding the sources and control of defects which contribute to semiconductor functionality and reliability losses. Such defects may arise from several sources. Typical defect sources include semiconductor manufacturing environments, manufacturing processes, process tooling and materials.
With regard to defects whose sources derive from manufacturing processes and materials, it is well known in the art that several types of defects may be formed through the process of implanting dopant ions into semiconductor substrates to form active semiconductor regions. It is also well known that the high ion implant doses required for formation of many advanced semiconductor circuit components simultaneously make amorphous the crystalline silicon semiconductor substrate into which the dopant ions are implanted. Upon subsequent annealing to recrystallize the amorphous region, latent defects are formed or appear at locations within or adjoining the recrystallized region.
Defects which are incident to annealing and recrystallization of amorphous ion implanted semiconductor substrates fall into three categories. The first two categories are Projected Range Defects (PRDs) and End of Range Defects (ERDs). These defects appear as dislocation loops within the depth of a semiconductor substrate which has been ion implanted and recrystallized. The location and density of these defects derives from the energy and dose of the implanting ions which caused the initial crystalline to amorphous transition of the semiconductor substrate.
The third category of defect related to recrystallization of a silicon semiconductor substrate made amorphous through ion implantation is the Mask Edge Defects (MEDs). In contrast to PRDs and ERDs, MEDs are defects typically localized to the surface of the recrystallized semiconductor substrate. In particular, MEDs are formed at locations where a recrystallizing silicon substrate surface adjoins another structure on the surface of the silicon substrate. A common structure adjoining which an MED may be formed is a gate spacer oxide structure. Gate spacer oxides are formed to insulate the gate electrode edge surfaces from the adjoining source/drain electrodes in field effect transistor structures. When formed in this location, an MED is commonly referred to as a gate spacer MED. It is towards the elimination of these gate spacer MEDs that the present invention is directed.
Schematic diagrams which illustrate the formation of gate spacer MEDs are shown in FIG. 1a, FIG. 1b, FIG. 2a and FIG. 2b. FIG. 1a and FIG. 1b. show the formation of gate spacer MEDs within a field effect transistor structure which possesses no screen oxide layer. FIG. 2a and FIG. 2b show the formation of gate spacer MEDs within an analogous field effect transistor structure having a screen oxide through which source/drain electrodes are ion implanted.
In FIG. 1a, FIG. 1b, FIG. 2a and FIG. 2b, a semiconductor substrate 10 has formed upon its surface a gate electrode 12 which is separated from the semiconductor substrate 10 by a gate oxide 14. On opposite sides of the gate electrode 12 and the gate oxide 14 are formed gate spacer oxides 16 which insulate the gate electrode 12 from source/drain electrodes 18. The source/drain electrodes 18 in FIG. 1a and FIG. 2a are made amorphous through a high dose ion implant. The field effect transistor structures of FIG. 2a and FIG. 2b additionally illustrate a pair of screen oxide layers 20 which absorb some of the damage of the high dose implanting ions which form the source/drain electrodes 18. FIG. 1b and FIG. 2b show the formation of gate spacer mask edge defects 22 within the semiconductor substrate 10 at the juncture with the gate spacer oxides 16 when the amorphous source/drain electrodes 18 of FIG. 1a and FIG. 2a are recrystallized.
The presence and the mechanism of formation of MEDs has been discussed in the art. For example, Cerva and Kusters, "Defect Formation in Silicon at a Mask Edge During Crystallization of an Amorphous Implantation Layer," 66 J. Appl. Physics (10) 4723 (1989) discuss the role of silicon substrate crystallographic planes upon defects formation when arsenic implanted amorphous silicon semiconductor substrates are recrystallized. From their observations, Cerva and Kusters conclude that mask edge type defects are an inevitable consequence of recrystallization of amorphous silicon semiconductor areas which have sharply curved geometries.
Consistent with the observations of Cerva and Kusters, Tamura, et al. "Mask Size Defects of Lattice Defects Generated by B- and As-Implantation Into Submicron Si Areas," Nuclear Instr. and Methods in Phys. Research B37/38 329 (1989) also discuss mask edge defects formation for submicron arsenic ion implantation into silicon semiconductor substrates. Tamura, et al. observed that when teardrop shaped amorphous regions are formed under mask edges, MEDs were formed under those mask edges after annealing those amorphous regions.
Amplifying the disclosure of Tamura, et al. is the disclosure of Horiuchi, et al., "Three-Dimensional Solid-Phase-Epitaxial Regrowth From As+-Implanted Si," 65 J. Appl. Phys. (6) 2238 (1989). Horiuchi, et al. further discuss the mechanisms associated with the formation of MEDs in silicon substrates implanted with arsenic ions. Horiuchi, et al. also observed that differences in applied stress due to differences in mask material have little effect upon MED formation at the edges of those masks. Rather, the substrate orientation and mask pattern direction play key roles in MED formation. Horiuchi, et al. also demonstrate that providing arc shaped corners to amorphous ion implanted areas on a (100) silicon wafer with a (110) mask pattern direction will eliminate mask edge defects when the amorphous ion implanted areas of that wafer are annealed and recrystallized.
Thus, the prior art illustrates both the existence of mask edge defects in arsenic implanted amorphous silicon semiconductor substrates and a general method by which those defects may be avoided. Absent from the prior art, however, is a disclosure of specific methods and materials by which mask edge defects may be avoided upon recrystallizing silicon semiconductor substrates which have been made amorphous through implanting of high doses of dopant ions.